The present invention relates to a semiconductor design technology, and in particular, to a path through which a clock swinging at a current mode logic (CML) level is transmitted in a semiconductor memory device. More particularly, the invention relates to a multiplexing of a path through which a clock swinging at a CML level is transmitted in a semiconductor memory device.
Generally, a semiconductor memory device uses a signal swinging at a CML level in an input/output (I/O) interface of a high frequency signal such as a clock. A CML level is a voltage level of a range defined by a predefined DC voltage level. A signal swinging at a CML level is a signal that toggles at a predefined frequency between a maximum voltage level (Vmax) and a minimum voltage level (Vmin) of a CML level, based on a reference voltage level within a CML level.
For example, even though a power supply voltage (VDD) level of a device for inputting/outputting a signal swinging at a CML level is 1.5 V and a ground voltage (VSS) level is 0 V, the CML level can be defined as 1.0 V instead of 1.5 V. A reference voltage level of the CML level is 1.25 V, and a signal swinging at the CML level toggles at a predefined frequency in such a state that it has a swing width of 0.5 V with respect to 1.25 V.
As described in the above example, the CML level is designed such that its magnitude is smaller than that of a voltage level region due to a difference between a power supply voltage (VDD) level and a ground voltage (VSS) level of a device for inputting/outputting a signal swinging at a CML level. This is because the signal swinging at the CML level is mainly a clock having a high frequency.
That is, the CML level is designed such that it can be stably transmitted even in the clock having a high frequency more than Giga hertz or tens of Giga hertz. However, since the magnitude of the CML level is relatively small, the swing width of the signal swinging at the CML level is relatively small. Therefore, the signal swinging at the CML level cannot be used as data whose logic level is determined according to voltage level variation. That is, the signal swinging at the CML level is suitable for the clock having a high frequency, but it is unsuitable for the data whose logic level is determined according to voltage level variation.
Therefore, a data input/output device uses the signal swinging at the CMOS level having a relatively large swing width, instead of the signal swinging at the CML level.
The CMOS level means a voltage level due to a difference between the power supply voltage (VDD) level and the ground voltage (VSS) level. The signal swinging at the CMOS level is a signal that toggles at a predefined frequency between a maximum voltage level (Vmax) and a minimum voltage level (Vmin) of a CMOS level, based on a reference voltage level within a CMOS level, that is, half of a voltage level between the power supply voltage (VDD) level and the ground voltage (VSS) level.
As described in the above example, in the case of the CMOS level, even though the power supply voltage (VDD) level is 1.5 V and the ground voltage (VSS) level is 0 V, voltage levels of 1.5 V and 1.0 V are specified as the CML level and thus the swing width of the signal swinging at the CML level may be 0.5 V. In the case of the CMOS level, if the power supply voltage (VDD) level is 1.5 V and the ground voltage (VSS) level is 0 V, the voltage levels of 1.5 V and 0 V are determined as the CMOS level and thus the swing width of the signal swinging at the CMOS level is always 1.5 V.
Therefore, the swing width of the signal swinging at the CMOS level is larger than that of the signal swinging at the CML level. This means that the signal swinging at the CMOS level can be suitably used as the data whose logic level is determined according to the voltage level.
For reference, as described above, it is usual that the signal swinging at the CML level toggles at a small swing width at the high frequency. Therefore, there is a high probability that the phase of the signal will be distorted or the voltage level thereof will be varied due to noise generated during transmission. Upon transmission of the signal swinging at the CML level, the signal is divided into two signals having opposite phases and the two signals are simultaneously transmitted.
On the contrary, it is usual that the signal swinging at the CMOS level toggles at a large swing width at a low frequency. Therefore, there is a low probability that the phase of the signal will be distorted and the voltage level thereof will be varied due to noise generated during transmission. Upon transmission of the signal swinging at the CMOS level, the signal is solely transmitted. In some cases, like the signal swinging at the CML level, the signal swinging at the CMOS level is divided into two signals having opposite phases and the two signals are simultaneously transmitted.
FIG. 1 illustrates a circuit for generating or transmitting a signal swinging at a CML level and a circuit for generating and transmitting a signal swinging at a CMOS level in a conventional semiconductor memory device.
It will be assumed that the signals CML_SGI and CML_SIGB swinging at the CML level and the signals CMOS_SIG and CMOS_SIGB swinging at the CMOS level are respectively divided into two signals having opposite phases and then simultaneously transmitted. Referring to FIG. 1, the circuit 100 for generating or transmitting the signals CML_SIG and CML_SIGB swinging at the CML level includes a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and first and second resistors R1 and R2. The first NMOS transistor N1 has a gate receiving a positive input signal INPUT_SIG, a drain connected to a negative output node OUT_NDB, and a source connected to a common node COMN, and adjusts an amount of current I1 flowing between the negative output node OUT_NDB and the common node COMN in response to the positive input signal INPUT_SIG. The second NMOS transistor N2 has a gate receiving a negative input signal INPUT_SIGB, a drain connected to a positive output node OUT_ND, and a source connected to the common node COMN, and adjusts an amount of current I2 flowing between the positive output node OUT_ND and the common node COMN in response to the negative input signal INPUT_SIGB. The third NMOS transistor N3 has a gate receiving a CML bias voltage CML_BIAS, a drain connected to the common node COMN, and a source connected to a ground voltage (VSS) terminal, and adjusts an amount of current I3 flowing between the common node COMN and the ground voltage (VSS) terminal in response to the CML bias voltage CML_BIAS, thereby adjusting an amount of sinking current I3 flowing out from the common node COMN. The first resistor R1 is connected between a power supply voltage (VDD) terminal and the negative output node OUT_NDB to adjust the swing width of the signal CML_SIGB output through the negative output node OUT_NDB and swinging at the CML level. The second resistor R2 is connected between the power supply voltage (VDD) terminal and the positive output node OUT_ND to adjust the swing width of the signal CML_SIG output through the positive output node OUT_ND and swinging at the CML level. The first and second resistors R1 and R2 have the same resistance.
An operation of the circuit 100 for generating or transmitting the signals CML_SIG and CML_SIGB swinging at the CML level in the conventional semiconductor memory device.
First, the positive input signal INPUT_SIG and the negative input signal INPUT_SIGB have opposite phases. Also, the CML bias signal CML_BIAS always has a logic high level. Therefore, the third NMOS transistor N3 is always turned on to discharge a predetermined amount of current from the common node COMN to the ground voltage (VSS) terminal. In such a state, if the voltage level of the positive input signal INPUT_SIG increases to turn on the first NMOS transistor N1, the voltage level of the negative input signal INPUT_SIGB decreases to turn off the second NMOS transistor N2. Thus, a predefined amount of current I1 flows from the negative output node OUT_NDB to the common node COMN, but a current I2 does not flow from the positive output node OUT_ND to the common node COMN.
That is, an amount of current I1 flowing from the negative output node OUT_NDB to the common node COMN is equal to an amount of current I3 flowing from the common node COMN to the ground voltage (VSS) terminal.
Consequently, the voltage level of the signal CML_SIGB output through the negative output node OUT_NDB and swinging at the CML level decreases, and the voltage level of the signal CML_SIG output through the positive output node OUT_ND and swinging at the CML level increases.
On the contrary, if the voltage level of the positive input signal INPUT_SIG decreases to turn off the first NMOS transistor N1, the voltage level of the negative input signal INPUT_SIGB increases to turn on the second NMOS transistor N2. Therefore, the current I1 does not flow from the negative output node OUT_NDB to the common node COMN, but a predefined amount of current I2 continuously flows from the positive output node OUT_ND to the common node COMN.
That is, an amount of current I2 flowing from the positive output node OUT_ND to the common node COMN is equal to an amount of current I3 flowing from the common node COMN to the ground voltage (VSS) terminal.
Consequently, the voltage level of the signal CML_SIGB output through the negative output node OUT_NDB and swinging at the CML level increases, and the voltage level of the signal CML_SIG output through the positive output node OUT_ND and swinging at the CML level decreases.
The decreasing degrees of the voltage levels of the signals CML_SIG and CML_SIGB swinging at the CML level are changed according to the resistances of the first and second resistors R1 and R2. This is because that the degrees determining the decreasing states of the voltage levels of the signals CML_SIG and CML_SIGB swinging at the CML levels may be changed according to potentials varying while the current I1 or I2 continuously flowing from the power supply voltage (VDD) terminal through the positive output node OUT_NDB or the negative output node OUT_ND to the ground voltage (VSS) terminal are passing through the first resistor R1 and the first and third NMOS transistors N1 and N3 or the second resistor R2 and the second and third NMOS transistors N2 and N3.
Specifically, even though the first NMOS transistor N1 and the third NMOS transistor N3 are sequentially turned on by the input signal INPUT_SIG and the CML bias signal CML_BIAS, or the second NMOS transistor N2 and the third NMOS transistor N3 are sequentially turned on by the input signal INPUT_SIGB and the CML bias signal CML_BIAS, the circuit 100 may have a very small resistance component due to the turned-on state of the transistors.
Therefore, the voltage levels of the signals CML_SIG and CML_SIGB swinging at the CML levels are determined by a voltage division law that is formed while the current I1 flows through the first resistor R1, the first NMOS transistor N1 and the third NMOS transistor N3. Also, the voltage levels of the signals CML_SIG and CML_SIGB swinging at the CML levels are determined by a voltage division law that is formed while the current I2 flows through the second resistor R2, the second NMOS transistor N2 and the third NMOS transistor N3.
Since the first resistor R1 and the second resistor R2 have the same resistance, the voltage levels of the signals CML_SIG and CML_SIGB swinging at the CML level are relatively closer to the ground voltage (VSS) level as the resistances of the first resistor R1 and the second resistor R2 become larger. As the resistances of the first resistor R1 and the second resistor R2 become smaller, the voltage levels of the signals CML_SIG and CML_SIGB swinging at the CML level are relatively far from the ground voltage (VSS) level. That is, as the resistances of the first resistor R1 and the second resistor R2 become larger, the swing widths of the signals CML_SIG and CML_SIGB swinging at the CML level are relatively larger. As the resistances of the first resistor R1 and the second resistor R2 become smaller, the swing widths of the signals CML_SIG and CML_SIGB are relatively smaller.
Meanwhile, the increasing degrees of the voltage levels of the signals CML_SIG and CML_SIGB swinging at the CML level are determined in a state that the currents do not continuously flow through the first resistors R1 and the second resistor R2. Therefore, when voltage levels of the signals CML_SIG and CML_SIGB swinging at the CML level are increased, they are almost equal to the power supply voltage (VDD) level.
A circuit 120 for generating or transmitting the signals CMOS_SIG and CMOS_SIGB swinging at a CMOS level in the conventional semiconductor memory device includes a first PMOS transistor P1, a first NMOS transistor N4, a second PMOS transistor P2, an a second NMOS transistor N5. The first PMOS transistor P1 has a gate receiving the positive input signal INPUT_SIG, a source connected to the power supply voltage (VDD) terminal, and a drain connected to a first driving node DRND1, and adjusts an amount of current I4 flowing through the power supply voltage (VDD) terminal and the first driving node DRND1 in response to the positive input signal INPUT_SIG. The first NMOS transistor N4 has a gate receiving the positive input signal INPUT_SIG, a drain connected to the first driving node DRND1, and a source connected to the ground voltage (VSS) terminal, and adjusts an amount of current I5 flowing between the first driving node DRND1 and the ground voltage (VSS) terminal in response to the positive input signal INPUT_SIG. The second PMOS transistor P2 has a gate receiving the negative input signal INPUT_SIGB, a source connected to the power supply voltage (VDD) terminal, and a drain connected to a second driving node DRND2, and adjusts an amount of current I6 flowing between the power supply voltage (VDD) terminal and the second driving node DRND2 in response to the negative input signal INPUT_SIGB. The second NMOS transistor N5 has a gate receiving the negative input signal INPUT_SIGB, a drain connected to the second driving node DRND2, a source connected to the ground voltage (VSS) terminal, and adjusts an amount of current I7 flowing between the second driving node DRND2 and the ground voltage (VSS) terminal in response to the negative input signal INPUT_SIGB.
An operation of the circuit 120 for generating or transmitting the signals CMOS_SIG and CMOS_SIGB swinging at the CMOS level in the above-described semiconductor memory device will be described below.
First, the positive input signal INPUT_SIG and the negative input signal INPUT_SIGB have opposite phases.
Therefore, when the voltage level of the positive input signal INPUT_SIG increases to turn off the first PMOS transistor P1 and turn on the first NMOS transistor N4, the voltage level of the negative input signal INPUT_SIGB decreases to turn on the second PMOS transistor P2 and turn off the second NMOS transistor N5.
Thus, a predefined amount of the current I5 flows from the first driving node DRND1 to the ground voltage (VSS) terminal, but the current I4 does not flow from the power supply voltage (VDD) terminal to the first driving node DRND1.
Likewise, a predefined amount of the current I6 flows from the power supply voltage (VDD) terminal to the second driving node DRND2, but the current I7 does not flow from the second driving node DRND2 to the ground voltage (VSS) terminal.
Therefore, the voltage level of the first driving node DRND1 falls to a level substantially equal to the ground voltage (VSS) level, and the voltage level of the second driving node DRND2 rises to a level substantially equal to the power supply voltage (VDD) level.
The predefined amount of the current I5 flows from the first driving node DRND1 to the ground voltage (VSS) terminal only until the voltage level of the first driving node DRND1 falls to the level substantially equal to the ground voltage (VSS) level, and it does not flow any more when the voltage level of the first driving node DRND1 falls to the level substantially equal to the ground voltage (VSS) level. That is, the predefined amount of the current I5 flowing from the first driving node DRND1 to the ground voltage (VSS) terminal is a current that instantaneously flows when the voltage level of the positive input signal INPUT_SIG rises.
Likewise, the predefined amount of the current I6 flows from the power supply voltage (VDD) terminal to the second driving node DRND2 only until the voltage level of the second driving node DRND2 rises to the level substantially equal to the power supply voltage (VDD) level, and it does not flow any more when the voltage level of the second driving node DRND2 rises to the level substantially equal to the power supply voltage (VDD) level. That is, the predefined amount of the current I6 flowing from the power supply voltage (VDD) terminal to the second driving node DRND2 is a current that instantaneously flows when the voltage level of the negative input signal INPUT_SIGB falls.
When the voltage level of the positive input signal INPUT_SIG decreases to turn on the first PMOS transistor P1 and turn off the first NMOS transistor N4, the voltage level of the negative input signal INPUT_SIGB increases to turn off the second PMOS transistor P2 and the turn on the second NMOS transistor N5.
Thus, the current I5 does not flow from the first driving node DRND1 to the ground voltage (VSS) terminal, but the predefined amount of the current I4 flows from the power supply voltage (VDD) terminal to the first driving node DRND1.
Likewise, the current I6 does not flow from the power supply voltage (VDD) terminal to the second driving node DRND2, but the predefined amount of the current I7 flows from the second driving node DRND2 to the ground voltage (VSS) terminal.
Therefore, the voltage level of the second driving node DRND2 falls to a level substantially equal to the ground voltage (VSS) level, and the voltage level of the first driving node DRND1 rises to a level substantially equal to the power supply voltage (VDD) level.
In this case, the predefined amount of the current I4 flows from the power supply voltage (VDD) terminal to the first driving node DRND1 only until the voltage level of the first driving node DRND1 rises to the level substantially equal to the power supply voltage (VDD) level, and it does not flow any more when the voltage level of the first driving node DRND1 rises to the level substantially equal to the power supply voltage (VDD) level. That is, the predefined amount of the current I4 flowing from the power supply voltage (VDD) terminal to the first driving node DRND1 is a current that instantaneously flows when the voltage level of the positive input signal INPUT_SIG falls.
Likewise, the predefined amount of the current I7 flows from the second driving node DRND2 to the ground voltage (VSS) terminal only until the voltage level of the second driving node DRND2 falls to the level substantially equal to the ground voltage (VSS) level, and it does not flow any more when the voltage level of the second driving node DRND2 falls to the level substantially equal to the ground voltage (VSS) level. That is, the predefined amount of the current I7 flowing from the second driving node DRND2 to the ground voltage (VSS) terminal is a current that instantaneously flows when the voltage level of the negative input signal INPUT_SIGB rises.
FIG. 2 is a graph for comparing an amount of current consumed according to variation of an operating frequency in the circuit for generating or transmitting the signals swinging at the CML level and the circuit for generating or transmitting the signals swinging at the CMOS level in the conventional semiconductor memory device of FIG. 1.
It can be seen from FIG. 2 that the circuit 100 for generating or transmitting the signals CML_SIG and CML_SIGB swinging at the CML level in the conventional semiconductor memory device consumes a constant amount of current, without regard to the variation of the operating frequency.
On the contrary, it can be seen that the circuit 120 for generating or transmitting the signals CMOS_SIG and CMOS_SIGB swinging at the CMOS level consumes a different amount of current according to the variation of the operating frequency.
First, the following description will be made on the principle that the circuit 100 for generating or transmitting the signals CML_SIG and CML_SIGB swinging at the CML level consumes a constant amount of current, without regard to the variation of the operating frequency.
Since the input signals are divided into the positive and negative input signals INPUT_SIG and INPUT_SIGB having opposite phases, one of the first NMOS transistor N1 and the second NMOS transistor N2 operating in response to the input signals INPUT_SIG and INPUT_SIGB is turned on, while the other is turned off. That is, the first NMOS transistor N1 and the second NMOS transistor N2 are controlled to operate oppositely.
At this point, since the sizes of the first NMOS transistor N1 and the second NMOS transistor N2 are equal to each other, a total amount of the currents I1 and I2 supplied from power supply voltage (VDD) terminal to the common node COMN is not varied, without regard to the variation in the voltage levels of the input signals INPUT_SIG and INPUT_SIGB or the variation in the voltage levels of the signals CML_SIG and CML_SIGB swinging at the CML level.
In addition, since the CML bias signal CML_BIAS always maintains the constant voltage level, the third NMOS transistor N3 is always maintained in the turned-on state when power is supplied to the semiconductor memory device. Therefore, the third NMOS transistor N3 can discharge a constant amount of current from the common node COMN to the ground voltage (VSS) terminal.
In this way, a constant amount of current I1 or I2 is always supplied to the common node COMN, without regard to the variation in the voltage levels of the input signals INPUT_SIG and INPUT_SIGB, and an amount of the current I3 discharged from the common node COMN to the ground voltage (VSS) terminal is constant. Thus, the voltage levels of the signals CML_SIG and CML_SIGB swinging at the CML level are varied according to the variation in the voltage levels of the input signals INPUT_SIG and INPUT_SIGB, but a total amount of current consumed is not varied.
For example, a constant amount of current is always consumed, even though the positive input signal INPUT_SIG changes from a logic low level to a logic high level, or from a logic high level to a logic low level, or the positive input signal INPUT_SIG maintains a logic low level or a logic high level.
Therefore, the circuit 100 for generating or transmitting the signals CML_SIG and CML_SIGB swinging at the CML level consumes a constant amount of current, even though the voltage levels of the input signals INPUT_SIG and INPUT_SIGB are in a high speed frequency state or a low speed frequency state.
The following description will be made on the principle that the circuit 120 for generating or transmitting the signals CMOS_SIG and CMOS_SIGB swinging at the CMOS level consumes a different amount of current according to the variation of the operating frequency.
First, the first PMOS transistor P1 and the first NMOS transistor N4 operating in response to the positive input signal INPUT_SIG will be explained. When the voltage level of the positive input signal INPUT_SIG decreases to a level lower than a predefined voltage level and thus the first PMOS transistor P1 is turned on, the first NMOS transistor N4 must be turned off. When the voltage level of the positive input signal INPUT_SIG increase to a level higher than the predefined voltage level and thus the first PMOS transistor P1 is turned off, the first NMOS transistor N4 must be turned on.
That is, the first PMOS transistor P1 and the first NMOS transistor N4 operates oppositely, but there cannot exist a direct current path flowing from the power supply voltage (VDD) terminal to the ground voltage (VSS) terminal.
Therefore, in a state that the first PMOS transistor P1 is turned on and the first NMOS transistor N4 is turned off, there exists the current I4 supplied from the power supply voltage (VDD) terminal to the first driving node DRND1 until the voltage level of the first driving node DRND1 is equal to the power supply voltage (VDD) level. In this case, the current I5 does not flow from the first driving node DRND1 to the ground voltage (VSS) terminal.
In addition, if the voltage level of the first driving node DRND1 is equal to the power supply voltage (VDD) level, the current I4 flowing from the power supply voltage (VDD) terminal to the first driving node DRND1 also disappears.
In a state that the first PMOS transistor P1 is turned off and the first NMOS transistor N4 is turned on, there exists the current I5 supplied from the first driving node DRND1 to the ground voltage (VSS) terminal until the voltage level of the first driving node DRND1 is equal to the ground voltage (VSS) level. In this case, the current I4 does not flow from the power supply voltage (VDD) terminal to the first driving node DRND1.
In addition, if the voltage level of the first driving node DRND1 is equal to the ground voltage (VSS) level, the current I5 flowing from the first driving node DRND1 to the ground voltage (VSS) terminal also disappears.
At this point, the current I5 flowing from the first driving node DRND1 to the ground voltage (VSS) terminal corresponds to the current I4 that is supplied from the power supply voltage (VDD) terminal to the first driving node DRND1 in the previous operation and stays at the first driving node DRND1, and then is discharged to the ground voltage (VSS) terminal. Therefore, an actually consumed current is the current I4 that has been supplied from the power supply voltage (VDD) terminal to the first driving node DRND1.
This phenomenon also occurs at the second PMOS transistor P2 and the second NMOS transistor N5 operating in response to the negative input signal INPUT_SIGB. However, a timing at which the current is actually consumed is different.
In the circuit 120 for generating or transmitting the signals CMOS_SIG and CMOS_SIGB swinging at the CMOS level, there exists only a direct current consumption for varying the voltage levels of the signals CMOS_SIG and CMOS_SIGB swinging at the CMOS level, which are output at a time point when the voltage levels of the input signals INPUT_SIG and INPUT_SIGB are varied.
For example, at the time when the positive input signal INPUT_SIG changes from a logic high level to a logic low level, there exists only a current consumption for changing the negative signal CMOS_SIGB from a logic low level to a logic high level. There exist no current consumption when the negative signal CMOS_SIGB maintains a logic high level or changes to a logic low level.
Therefore, the circuit 120 for generating or transmitting the signals CMOS_SIG and CMOS_SIGB swinging at the CMOS level consumes a relatively large amount of current in a high speed frequency state, where the voltage level of the input signals INPUT_SIG and INPUT_SIGB are varied at high speed, and consumes a relatively small amount of current in a low speed frequency state, where the voltage levels of the input signals INPUT_SIG and INPUT_SIGB are varied at low speed.
Meanwhile, it is usual that the semiconductor device, especially a synchronous dynamic random access memory (SDRAM) outputs data in synchronization with a clock. Likewise, it is usual that external data are input to the SDRAM in synchronization with a clock.
At this point, since data input from the outside of the SDRAM has been already synchronized with the clock, the SDRAM need not perform a special synchronization process.
However, when data are output to the outside of the SDRAM, an operation of synchronizing the data with the clock should be performed because the data is not synchronized with the clock due to the internal operation of the SDRAM.
However, due to a swing width difference between the signal swinging at the CML level and the signal swinging at the CMOS level, an error may occur when the data is directly synchronized with the clock. Upon the synchronization operation, the clock swinging at the CML level needs to be converted into the clock swinging at the CMOS level.
Therefore, an output driver of the SDRAM must include a CML-to-CMOS converter for converting the signal swinging at the CML level into the signal swinging at the CMOS level.
That is, after the clock swinging at the CML level is transmitted to the data output driver of the SDRAM, it is converted into the signal swinging at the CMOS level and synchronizes the data.
FIG. 3 is a block diagram illustrating a path through which a signal swinging at a CML level is transmitted to a data output driver in a conventional semiconductor memory device.
Referring to FIG. 3, a positive clock CML_CLK and a negative clock CML_CLKB input through a positive clock input pad CLK_IN_PAD and a negative clock input pad CLK_IN_PADB and swinging at the CML level are transmitted through a plurality of CML clock transfer units 300 and 310 to a clock converting unit 320. Then, the positive clock CML_CLK and the negative clock CML_CLKB are converted into clocks CMOS_CLK and CMOS_CLKB swinging at the CMOS level by a clock converting unit 320, and then transmitted to a data output driver 340.
The data output driver 340 transfers output data of a core region 360 to a data output pad 380 in response to the clocks CMOS_CLK and CMOS_CLKB swinging at the CMOS level.
That is, the positive clock CML_CLK and the negative clock CML_CLKB swinging at the CML level are input through the positive clock input pad CLK_IN_PAD and the negative clock input pad CLK_IN_PADB and transmitted while repeating a relatively long path through the plurality of CML clock transfer units 300 and 310. The positive clock CML_CLK and the negative clock CML_CLKB are converted into the signals swinging at the CMOS level by the clock converting unit 320 immediately before they reach the data output driver 340.
When transferring the positive clock CML_CLK and the negative clock CML_CLKB swinging at the CML level, they continuously maintain a state of swinging at the CML level. However, such a structure may cause a problem that increase an amount of current consumed according to frequencies of the positive clock CML_CLK and the negative clock CML_CLKB swinging at the CML level.
Specifically, as described above with reference to FIG. 2, when transferring the signals swinging at the CML level, a constant amount of current is consumed, without regard to frequencies of the signals swinging at the CML level.
On the other hand, when transferring the signals swinging at the CMOS level, an amount of current consumed is varied according to frequencies of the signals swinging at the CMOS level. That is, the current consumption is relatively small when the frequencies of the signals swinging at the CMOS level are low, and the current consumption is relatively large when the frequencies of the signals swinging at the CMOS level are high.
Therefore, as illustrated in FIG. 2, in the case of transferring the low frequency signal, the current consumption can be reduced by transferring the signal in a state of swinging at the CMOS level. In the case of transferring the high frequency signal, the current consumption can be reduced by transferring the signal in a state of swinging at the CML level.
Since it is usual that the input clock signal has a high frequency, the current consumption can be reduced by maintaining the clock signal in state of swinging at the CML level inside the semiconductor memory device and converting it into the CMOS level immediately before it reaches the data output driver 340.
However, this structure is configured on the assumption that the input clock signal has a high frequency. If the input clock signal has a low frequency, the current consumption will be increased.
That is, the structure of FIG. 3 can reduce the current consumption only when the semiconductor memory device operates at a normal mode. However, the current consumption is increased at a low speed operation test mode for testing the semiconductor memory device by using a low frequency clock, at a low power test mode for multi die test, and under a low power or low speed frequency environment, such as a low power mode that is widely used in a mobile environment.
Therefore, the semiconductor memory device intended to be used under the low power or low speed frequency environment cannot be tested normally, and the test time increases. In particular, it is impossible to normally implement the mobile environment where the semiconductor memory device should operate at a low power mode.